DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 537

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the
SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and
SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
In the H8/3052BF, the SINV bit inverts only the data bits D7 to D0. The parity bit is not inverted,
so the O/E bit in SMR must be set to odd parity mode. This applies in both transmitting and
receiving.
Direct convention (SDIR = SINV = O/E = 0)
In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0.
Characters are transmitted and received LSB-first. In the example above the first character data
is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
Inverse convention (SDIR = SINV = O/E = 1)
In the inverse convention, state A corresponds to the logic level 1, and state Z to the logic level
0. Characters are transmitted and received MSB-first. In the example above the first character
data is H'3F. Following the even parity rule designated for smart cards, the parity bit logic
level is 0, corresponding to state Z.
(Z)
(Z)
Ds
Ds
A
A
D0
D7
Z
Z
D1
D6
Z
Z
D2
D5
A
A
D3
D4
A
Z
D4
D3
Z
A
D5
D2
A
Z
Rev. 3.00 Mar 21, 2006 page 507 of 814
D6
D1
A
A
Section 14 Smart Card Interface
D7
D0
A
A
Dp
Dp
Z
Z
REJ09B0302-0300
(Z)
(Z)
State
State

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