DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 607

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800,
9,600 or 19,200 bps to operate the SCI properly.
Table 18.6 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is
Notes: 1. Use a host bit rate setting of 4800, 9600, or 19200 bps only. No other setting should be
Host Bit Rate
4800 bps
9,600 bps
19,200 bps
2. Although the H8/3052BF may also perform automatic bit rate adjustment with bit rate
used.
and system clock combinations other than those shown in table 18.6, a degree of error
will arise between the bit rates of the host and the H8/3052BF, and subsequent transfer
will not be performed normally. Therefore, only combinations of bit rate and system
clock within the ranges shown in table 18.6 can be used for boot mode execution.
Possible
Start
bit
System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible (MHz)
4 to 25
8 to 25
16 to 25
D0
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev. 3.00 Mar 21, 2006 page 577 of 814
D5
D6
D7
(1 or more bits)
REJ09B0302-0300
Section 18 ROM
High period
Stop
bit