DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 21

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2
8.3
8.4
8.5
8.6
Section 9 I/O Ports
9.1
9.2
Register Descriptions (Short Address Mode).................................................................... 191
8.2.1
8.2.2
8.2.3
8.2.4
Register Descriptions (Full Address Mode)...................................................................... 198
8.3.1
8.3.2
8.3.3
8.3.4
Operation........................................................................................................................... 206
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 234
8.4.11 NMI Interrupts and DMAC.................................................................................. 235
8.4.12 Aborting a DMA Transfer.................................................................................... 236
8.4.13 Exiting Full Address Mode .................................................................................. 237
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 238
Interrupts ........................................................................................................................... 239
Usage Notes ...................................................................................................................... 240
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
Overview........................................................................................................................... 245
Port 1................................................................................................................................. 249
9.2.1
Memory Address Registers (MAR) ..................................................................... 192
I/O Address Registers (IOAR) ............................................................................. 193
Execute Transfer Count Registers (ETCR).......................................................... 194
Data Transfer Control Registers (DTCR) ............................................................ 195
Memory Address Registers (MAR) ..................................................................... 198
I/O Address Registers (IOAR) ............................................................................. 199
Execute Transfer Count Registers (ETCR).......................................................... 199
Data Transfer Control Registers (DTCR) ............................................................ 201
Overview.............................................................................................................. 206
I/O Mode.............................................................................................................. 208
Idle Mode............................................................................................................. 210
Repeat Mode ........................................................................................................ 213
Normal Mode....................................................................................................... 217
Block Transfer Mode ........................................................................................... 220
DMAC Activation................................................................................................ 225
DMAC Bus Cycle ................................................................................................ 227
DMAC Multiple-Channel Operation ................................................................... 233
Note on Word Data Transfer................................................................................ 240
DMAC Self-Access ............................................................................................. 240
Longword Access to Memory Address Registers ................................................ 240
Note on Full Address Mode Setup ....................................................................... 240
Note on Activating DMAC by Internal Interrupts ............................................... 240
NMI Interrupts and Block Transfer Mode ........................................................... 242
Memory and I/O Address Register Values .......................................................... 242
Bus Cycle when Transfer Is Aborted ................................................................... 243
Overview.............................................................................................................. 249
.............................................................................................................. 245
Rev. 3.00 Mar 21, 2006 page xix of xxviii