DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 256

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 DMA Controller
Activation by External Request: If an external request (DREQ pin) is selected as an activation
source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output
pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level-
sensitive or edge-sensitive.
In short address mode and normal mode, an external request operates as follows. If edge sensing is
selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is
detected. If the next edge is input before the transfer is completed, the next transfer may not be
executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer
is completed. The bus is released temporarily after each byte or word has been transferred,
however. If the DREQ input goes high during a transfer, the transfer is suspended after the current
byte or word has been transferred. When DREQ goes low, the request is held internally until one
byte or word has been transferred. The TEND signal goes low during the last write cycle.
In block transfer mode, an external request operates as follows. Only edge-sensitive transfer
requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ input
is detected, a block of the specified size is transferred. The TEND signal goes low during the last
write cycle in each block.
Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and
continues until completed. Cycle-steal mode or burst mode can be selected.
In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word.
Normally, DMAC cycles alternate with CPU cycles.
In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higher-
priority bus request. If there is a higher-priority bus request, the bus is released after the current
byte or word has been transferred.
Rev. 3.00 Mar 21, 2006 page 226 of 814
REJ09B0302-0300

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