DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 479

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by
Bit 7: TDRE
0
1
Bit 6: RDRF
0
1
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
Description
TDR contains valid transmit data
[Clearing conditions]
TDR does not contain valid transmit data
[Setting conditions]
Description
RDR does not contain new receive data
[Clearing conditions]
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR.
Software reads TDRE while it is set to 1, then writes 0.
The DMAC writes data in TDR.
The chip is reset or enters standby mode.
The TE bit in SCR is cleared to 0.
TDR contents are loaded into TSR, so new data can be written in TDR.
The chip is reset or enters standby mode.
Software reads RDRF while it is set to 1, then writes 0.
The DMAC reads data from RDR.
Section 13 Serial Communication Interface
Rev. 3.00 Mar 21, 2006 page 449 of 814
REJ09B0302-0300
(Initial value)
(Initial value)

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