DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 517

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear
No
No
No
both the TE bit and the RE bit to 0, then set both bits to 1.
Clear TE and RE bits to 0 in SCR
and clear RDRF flag to 0 in SSR
Start transmitting and receiving
Write transmit data in TDR and
Read receive data from RDR
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
Read TDRE flag in SSR
Read RDRF flag in SSR
End of transmitting and
RDRF = 1?
Figure 13.20 Sample Flowchart for Serial Transmitting
TDRE = 1?
ORER = 1?
receiving?
Initialize
End
No
Yes
Yes
Yes
Error handling
Yes
1
2
4
5
3
1. SCI initialization: the transmit data output
2. SCI status check and transmit data write:
3. Receive error handling: if a receive error
4. SCI status check and receive data read:
5. To continue transmitting and receiving serial
Section 13 Serial Communication Interface
function of the TxD pin and receive data
input function of the RxD pin are selected,
enabling simultaneous transmitting and
receiving.
read SSR, check that the TDRE flag is 1,
then write transmit data in TDR and clear
the TDRE flag to 0. Notification that the
TDRE flag has changed from 0 to 1 can also
be given by the TXI interrupt.
occurs, read the ORER flag in SSR, then
after executing the necessary error handling,
clear the ORER flag to 0. Neither
transmitting nor receiving can resume while
the ORER flag remains set to 1.
read SSR, check that the RDRF flag is 1,
then read receive data from RDR and clear
the RDRF flag to 0. Notification that the
RDRF flag has changed from 0 to 1 can also
be given by the RXI interrupt.
data: check the RDRF flag, read RDR, and
clear the RDRF flag to 0 before the MSB (bit
7) of the current frame is received. Also
check that the TDRE flag is set to 1,
indicating that data can be written, write data
in TDR, then clear the TDRE flag to 0 before
the MSB (bit 7) of the current frame is
transmitted. When the DMAC is activated by
a transmit-data-empty interrupt request (TXI)
to write data in TDR, the TDRE flag is
checked and cleared automatically. When
the DMA C is activated by a receive-data-full
interrupt request (RXI) to read RDR, the
RDRF flag is cleared automatically.
Rev. 3.00 Mar 21, 2006 page 487 of 814
REJ09B0302-0300