DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 312

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 I/O Ports
Rev. 3.00 Mar 21, 2006 page 282 of 814
REJ09B0302-0300
Port A
Port A pins
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TEND /TCLKB
PA /TP /TEND /TCLKA
Pin functions in modes 1, 2, and 5
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)/CS
PA (input/output)/TP (output)/TIOCB (input/output)/CS
PA (input/output)/TP (output)/TIOCA (input/output)/CS
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TEND (output)/TCLKB (input)
PA (input/output)/TP (output)/TEND (output)/TCLKA (input)
Pin functions in modes 3, 4, and 6
A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TEND (output)/TCLKB (input)
PA (input/output)/TP (output)/TEND (output)/TCLKA (input)
Pin functions in mode 7
PA
PA
PA
PA
PA
PA
PA
PA
20
Figure 9.10 Port A Pin Configuration
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(output)
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
7
6
5
4
3
2
1
0
1
0
2
2
1
1
0
0
21
22
23
20
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
/CS
/CS
/CS
(output)/TIOCB
(output)/TIOCA
(output)/TIOCB
(output)/TIOCA
(output)/TIOCB
(output)/TIOCA
(output)/TEND
(output)/TEND
4
5
6
1
0
1
0
1
0
2
2
1
1
0
0
2
2
1
1
0
0
2
1
1
0
0
(output)/TCLKB (input)
(output)/TCLKA (input)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)/TCLKD (input)
(input/output)/TCLKC (input)
21
22
23
4
5
6
(output)/CS
(output)/CS
(output)/CS
(output)
(output)
(output)
4
5
6
(output)
(output)
(output)