DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 14

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
21.2.2 AC Characteristics
Table 21.7 Timing of On-
Chip Supporting Modules
21.2.3 A/D Conversion
Characteristics
Table 21.8 A/D Converter
Characteristics
21.2.4 D/A Conversion
Characteristics
Table 21.9 D/A Converter
Characteristics
21.2.5 Flash Memory
Characteristics
Table 21.10 Flash
Memory Characteristics
A.1 Instruction List
Table A.1 Instruction Set
2. Arithmetic instructions
Rev. 3.00 Mar 21, 2006 page xii of xxviii
Page
639
640
641
642, 643
663
Revisions (See Manual for Details)
Condition A and Condition B deleted
Table and notes amended
Condition A and Condition B deleted
Table and notes amended
Condition A and Condition B deleted
Condition A and Condition B deleted
Table and notes amended
Table amended
Item
DMAC
ITU
Item
Reprogramming count
Data retention period
DAA Rd
Item
Conversion time
Notes: 1 The value is for
Notes: 6.
Mnemonic
7.
8.
2 The value is for
Minimum cycle value which guarantees all characteristics after reprogramming.
(Reprogram cycles from 1 to minimum value are guaranteed.)
Reference characteristics at 25˚C. (This is a indication that reprogram operation can
normally function up to this figure.)
Data retention characteristics when reprogaram performed correctly within
specification value including minimum data retention period.
DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
B
Rd8 decimal adjust
Rd8
Single edge
Both edges
Operation
13 MHz.
13 MHz.
Symbol Min
N
T
Symbol
t
t
t
t
t
t
t
t
t
DRQS
DRQH
TED1
TED2
TOCD
TICS
TCKS
TCKWH
TCKWL
DRP
WEC
Instruction Length (bytes)
2
Addressing Mode and
Min
5.36
100 *
10 *
Min
20
10
—
—
—
40
40
1.5
2.5
8
6
Conditions
Conditions
Typ
10.000 *
—
Max
—
—
50
50
50
—
—
—
—
Typ
—
Conditions
7
Max
—
—
—
I
Condition Code
Unit
ns
ns
t
t
H
cyc
scyc
Unit
Times
Years
N
—
Z
Max
Test
Conditions
Figure 21.16
Figure 21.24,
Figure 21.25
Figure 21.20
Figure 21.21
V
*
Notes
C
States
No. of
2
*1