DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 783

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SSR—Serial Status Register
Transmit data register empty
Note: Only 0 can be written, to clear the flag.
0
1
Receive data register full
Bit
Initial value
Read/Write
0
1
[Clearing conditions]
[Setting conditions]
data to be written in TDR.
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
*
[Clearing conditions]
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
The DMAC reads data from RDR.
Framing error (for SCI0)
0
1
Parity error
[Clearing conditions]
[Setting condition]
Framing error (stop bit is 0)
0
1
Reset or transition to standby mode.
Read FER when FER = 1, then write 0 in FER.
[Clearing conditions]
[Setting condition]
Parity error: (parity of receive data does
not match parity setting O/E bit in SMR)
Reset or transition to standby mode.
Read PER when PER = 1, then write 0
in PER.
R/(W)
TDRE
7
1
*
R/(W)
RDRF
6
0
*
Multiprocessor bit
0
1
ORER
R/(W)
Multiprocessor bit value in
receive data is 0
Multiprocessor bit value in
receive data is 1
5
0
*
FER/ERS
R/(W)
4
0
Error signal status (for smart card interface)
Transmit end
Overrun error
0
1
0
1
0
1
*
[Clearing conditions]
[Setting condition]
A low error signal is received.
[Clearing conditions]
[Setting conditions]
[Clearing conditions]
[Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
Reset or transition to standby mode.
Read ERS when ERS = 1, then write 0 in ERS.
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
Reset or transition to standby mode.
TE is cleared to 0 in SCR and FER/ERS is
TDRE is 1 when last bit of 1-byte serial character
cleared to 0.
is transmitted.
ORER.
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
Rev. 3.00 Mar 21, 2006 page 753 of 814
R/(W)
PER
3
0
*
Appendix B Internal I/O Register
Multiprocessor bit transfer
H'B4
TEND
0
1
R
2
1
Multiprocessor bit value in
transmit data is 0
Multiprocessor bit value in
transmit data is 1
MPB
R
1
0
REJ09B0302-0300
MPBT
R/W
0
0
SCI0