DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 171

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 6.19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
Figure 6.19 External-Bus-Released State (Two-State-Access Area during Read Cycle)
Address
bus
CS
Data bus
AS
HWR
BREQ
BACK
Note: n = 7 to 0
1
2
3
4, 5
6
n
,
RD
Low
BACK
BREQ
High
BREQ
,
LWR
BREQ
BREQ
signal goes low at end of CPU read cycle, releasing bus right to external bus master.
pin continues to be sampled while bus is released to external bus master.
signal goes high, ending bus-release cycle.
High
signal is sampled twice consecutively.
signal is sampled at rise of T state.
1
CPU cycles
Minimum 2 cycles
T
Address
1
T
1
2
2
3
External bus released
Rev. 3.00 Mar 21, 2006 page 141 of 814
High-impedance
High-impedance
High-impedance
High-impedance
High
4
Section 6 Bus Controller
5
REJ09B0302-0300
6
CPU cycles