DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 626

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
This is done to avoid the following operation states:
1. Generation of an NMI input during programming/erasing violates the program/erase
2. Vector-read cannot be carried out normally *
3. If an NMI input is generated during boot program execution, the normal boot mode sequence
Therefore, this LSI has conditions that exceptionally disable NMI inputs only in the on-board
programming mode. However, this does not assure normal programming/erasing and
microcomputer operation.
Thus, in the FWE application state, all requests, including NMI, inside and outside the
microcomputer, exception handling, and bus release must be restricted. NMI input is also
disabled *
E2 bit in FLMCR2, is retained during flash memory emulation by RAM.
Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area
Rev. 3.00 Mar 21, 2006 page 596 of 814
REJ09B0302-0300
algorithms and normal operation can not longer be assured.
programming/erasing and the microcomputer runs away as a result.
cannot be executed.
2. In this case, vector read is not performed normally for the following two reasons:
3. When the emulation function is used, NMI input is prohibited when the P1 bit or E1 bit
3
in the error-protected state and when the P1 bit or E1 bit in FLMCR1, or the P2 bit or
(H'FFDF10). (This branch occurs immediately after user program transfer was
completed.)
Therefore, after branching to RAM area, NMI input is enabled in states other than the
program/erase state. Thus, interrupt requests inside and outside the microcomputer
must be disabled until initial writing by user program (writing of vector table and NMI
processing program, etc.) is completed.
a. The correct value cannot be read even by reading the flash memory during
b. If a value has not yet been written to the NMI vector table, NMI exception handling
in FLMCR1, or the P2 bit or E2 bit in FLMCR2, is set to 1, in the same way as with
normal programming and erasing. The P1 and E1 bits and the P2 and E2 bits are
cleared by a reset (including a watchdog timer reset), in standby mode, when a high
level is not being input to the FWE pin, or when the SWE1 bit in FLMCR1 is 0, or the
SWE2 bit in FLMCR2 is 0, while a high level is being input to the FWE pin.
programming/erasing. (Value is undefined.)
will not be performed correctly.
2
during NMI exception handling during