DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 135

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.5.2
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
5.5.4
The specifications provide for the IRQnF flag to be cleared by first reading the flag while it is set
to 1, then writing 0 to it. However, there are cases in which the IRQnF flag is erroneously cleared,
preventing execution of interrupt exception handling, simply by writing 0 to the flag, without first
reading 1 from it. This occurs when the following conditions are fulfilled.
Setting Conditions
1. When using multiple external interrupts (IRQa, IRQb)
2. When different clearing methods are used for the IRQaF flag and IRQbF flag, with the IRQaF
3. IRQaF flag clears and bit operation command is being used for the IRQ status register (ISR) or
L1: EEPMOV.W
flag cleared by writing 0 to it, and the IRQbF flag cleared by hardware.
the ISR is being read in bytes; IRQaF flag’s bits clear and other bit values read in bits are
written in bytes.
MOV.W R4,R4
BNE
Notes on Use of External Interrupts
Instructions that Inhibit Interrupts
Interrupts during EEPMOV Instruction Execution
L1
Rev. 3.00 Mar 21, 2006 page 105 of 814
Section 5 Interrupt Controller
REJ09B0302-0300