DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 558

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
CH2
0
1
15.2.3
Bit
Initial value
Read/Write
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7E by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bits 6 to 1—Reserved: Read-only bits, always read as 1.
Rev. 3.00 Mar 21, 2006 page 528 of 814
REJ09B0302-0300
Bit 7: TRGE
0
1
A/D Control Register (ADCR)
Trigger enable
Enables or disables external triggering of A/D conversion
0
1
0
1
CH1
TRGE
Channel Selection
R/W
7
0
Description
A/D conversion cannot be externally triggered
A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
CH0
0
1
0
1
0
1
0
1
—
—
6
1
—
—
5
1
Single Mode
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
(Initial value)
Reserved bits
—
—
4
1
—
—
3
1
Description
—
—
2
1
Scan Mode
AN
AN
AN
AN
AN
AN
AN
AN
0
0
0
0
4
4
4
4
, AN
, AN
Reserved bit
Must not be set to 1
to AN
to AN
to AN
to AN
—
—
1
1
1
5
2
3
6
7
(Initial value)
—
—
0
0