DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 134

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.5
5.5.1
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
actually disabled until after execution of the instruction is completed. Thus, if an interrupt occurs
while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at
the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt
exception handling is carried out. If a higher-priority interrupt is also requested, however,
interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority
interrupt is ignored. This also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU.
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
Rev. 3.00 Mar 21, 2006 page 104 of 814
REJ09B0302-0300
Internal
address bus
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
Usage Notes
Contention between Interrupt Generation and Disabling
TIER write cycle by CPU
TIER address
IMIA exception handling

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