DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 707

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A.3
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-
bit bus width.
BSET #0, @FFFFC7:8
JSR @@30
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, S
Number of states = 2
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, S
Number of states = 2
Number of States Required for Execution
S
I
+ J
I
I
= 4 and S
= S
S
J
4 + 2
4 + 2
= S
J
+ K
K
L
= 4
= 3
3 = 14
4 + 2
S
K
+ L
4 = 24
S
L
+ M
Rev. 3.00 Mar 21, 2006 page 677 of 814
S
M
+ N
S
N
Appendix A Instruction Set
REJ09B0302-0300