DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 129

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1. If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
2. When the interrupt controller receives one or more interrupt requests, it selects the highest-
3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
5. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
6. Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
7. The vector address of the accepted interrupt is generated, and the interrupt service routine
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ
to IRQ
Figure 5.5 shows the transitions among the above states.
interrupt request is sent to the interrupt controller.
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
current instruction has been completed.
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
starts executing from the address indicated by the contents of the vector address.
Interrupt requests with priority level 0 are enabled when the I bit is cleared to 0, and disabled
when the I bit is set to 1.
Interrupt requests with priority level 1 are enabled when the I bit or UI bit is cleared to 0, and
disabled when the I bit and UI bit are both set to 1.
For example, if the interrupt enable bits of all interrupt requests are set to 1, and IPRA and
IPRB are set to H'20 and H'00, respectively (giving IRQ
over other interrupts), interrupts are enabled and disabled as follows:
a. If I = 0, all interrupts are enabled (priority order: NMI > IRQ
b. If I = 1 and UI = 0, only NMI, IRQ
c. If I = 1 and UI = 1, all interrupts are disabled except NMI.
5
interrupts and interrupts from the on-chip supporting modules.
2
, and IRQ
3
are enabled.
Rev. 3.00 Mar 21, 2006 page 99 of 814
2
and IRQ
2
Section 5 Interrupt Controller
> IRQ
3
interrupt requests priority
3
> IRQ
REJ09B0302-0300
0
...).
0