DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 363

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
0
1
2
3
4
Bit
Initial value
Read/Write
Note:
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in TIER.
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
*
Only 0 can be written, to clear the flag.
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
—
—
7
1
—
—
6
1
Reserved bits
Function
Indicates input capture, compare match, and overflow status
—
—
5
1
—
—
4
1
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Section 10 16-Bit Integrated Timer Unit (ITU)
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Rev. 3.00 Mar 21, 2006 page 333 of 814
Overflow flag
Status flag indicating
overflow or underflow
—
—
3
1
R/(W)
OVF
2
0
*
R/(W)
IMFB
1
0
REJ09B0302-0300
*
R/(W)
IMFA
0
0
*