DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 263

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.4.9
The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.
Table 8.12 shows the complete priority order.
Table 8.12 Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfers are requested on two or more channels simultaneously, or if a transfer on one channel
is requested during a transfer on another channel, the DMAC operates as follows.
1. When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
2. Once a transfer starts on one channel, requests to other channels are held pending until that
3. After each transfer in short address mode, and each externally-requested or cycle-steal transfer
4. After completion of a burst-mode transfer, or after transfer of one block in block transfer
Figure 8.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
starts a transfer on the highest-priority channel at that time.
channel releases the bus.
in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if
there is a transfer request for another channel, the DMAC requests the bus again.
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus
again.
DMAC Multiple-Channel Operation
Full Address Mode
Channel 0
Channel 1
Rev. 3.00 Mar 21, 2006 page 233 of 814
Priority
High
Low
Section 8 DMA Controller
REJ09B0302-0300

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