DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 19

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
Overview........................................................................................................................... 79
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 82
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 92
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 97
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 104
5.5.1
5.5.2
5.5.3
5.5.4
Overview........................................................................................................................... 109
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 112
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Features................................................................................................................ 79
Block Diagram ..................................................................................................... 80
Pin Configuration................................................................................................. 81
Register Configuration......................................................................................... 81
System Control Register (SYSCR) ...................................................................... 82
Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 83
IRQ Status Register (ISR).................................................................................... 89
IRQ Enable Register (IER) .................................................................................. 90
IRQ Sense Control Register (ISCR) .................................................................... 91
External Interrupts ............................................................................................... 92
Internal Interrupts................................................................................................. 93
Interrupt Exception Vector Table ........................................................................ 93
Interrupt Handling Process................................................................................... 97
Interrupt Exception Handling Sequence .............................................................. 102
Interrupt Response Time...................................................................................... 103
Contention between Interrupt Generation and Disabling..................................... 104
Instructions that Inhibit Interrupts........................................................................ 105
Interrupts during EEPMOV Instruction Execution .............................................. 105
Notes on Use of External Interrupts..................................................................... 105
Features................................................................................................................ 109
Block Diagram ..................................................................................................... 110
Pin Configuration................................................................................................. 111
Register Configuration......................................................................................... 112
Bus Width Control Register (ABWCR)............................................................... 112
Access State Control Register (ASTCR) ............................................................. 113
Wait Control Register (WCR).............................................................................. 114
Wait State Controller Enable Register (WCER) .................................................. 115
Bus Release Control Register (BRCR) ................................................................ 116
Chip Select Control Register (CSCR).................................................................. 118
.................................................................................................... 109
.......................................................................................... 79
Rev. 3.00 Mar 21, 2006 page xvii of xxviii