DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 276

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 I/O Ports
Table 9.1
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Rev. 3.00 Mar 21, 2006 page 246 of 814
REJ09B0302-0300
Port
Description
8-bit I/O port
Can drive
LEDs
8-bit I/O port
Input pull-up
MOS
Can drive
LEDs
8-bit I/O port P3
8-bit I/O port
Input pull-up
MOS
4-bit I/O port
Input pull-up
MOS
Can drive
LEDs
7-bit I/O port
o8-bit I/O
port
Port Functions
P1
A
P2
A
D
P4
D
P5
A
P6
P6
P6
P6
P6
P6
P6
P7
P7
P7
AN
7
15
19
15
7
7
7
7
7
3
6
5
4
3
2
1
0
7
6
5
to A
to D
5
/LWR,
/HWR,
/RD,
/AS
/BACK,
/BREQ,
/WAIT
/AN
/AN
to A
to A
to D
to P1
to P2
to P3
to P4
to P5
to P7
to AN
Pins
0
0
7
6
8
16
8
/DA
/DA
0
0
0
0
0
0
0
/
/
/
/
/
/
1
0
,
Address output pins (A
Address output pins (A
Data input/output (D
Data input/output (D
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
Address output (A
Bus control signal output (LWR, HWR, RD, AS)
Bus control signal input/output (BACK, BREQ, WAIT) and 3-
bit generic input/output
Analog input (AN
D/A converter, and generic input
Analog input (AN
Mode 1
Mode 2
7
5
, AN
19
to AN
15
7
to A
to D
Mode 3
6
to D
7
15
) to A/D converter, analog output (DA
0
to A
16
) to A/D converter, and generic input
to A
0
)
8
) and 8-bit generic input/output
)
0
)
8
)
Mode 4
Address output (A
to A
input
DDR = 0: generic
input
DDR = 1: address
output
Address output (A
to A
input
DDR = 0: generic
input
DDR = 1: address
output
Address output (A
to A
generic input
DDR = 0: generic
input
DDR = 1: address
output
Mode 5
0
8
16
) and generic
) and generic
) and 4-bit
Mode 6
7
15
19
1
, DA
Generic
input/
output
Generic
input/
output
Generic
input/
output
Generic
input/
output
Generic
input/
output
Generic
input/
output
Mode 7
0
) from