DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 536

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Smart Card Interface
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data.
14.3.4
Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 should always be set to the indicated value. The settings of the other bits will be described in this
section.
Table 14.3 Register Settings in Smart Card Interface
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Legend: — Unused bit.
Notes: 1. Lower 16 bits of the address.
Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.
In regular smart card mode, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the
O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smart card uses
the inverse convention. Bits CKS1 and CKS0 select the clock source of the built-in baud rate
generator. See section 14.3.5, Clock.
Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the
setting are given in section 14.3.5, Clock.
Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial
communication functions. For details, see section 13, Serial Communication Interface. The CKE1
and CKE0 bits select clock output. When the GM bit of the SMR is cleared to 0, to disable clock
output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR
is set to 1, clock output is enabled. Clock output is fixed at high or low.
Rev. 3.00 Mar 21, 2006 page 506 of 814
REJ09B0302-0300
designated interval, the receiving device returns the signal line to the high-impedance state.
The signal line is pulled back up to the high level through the pull-up resistor.
If it receives an error signal, it returns to step 2 and transmits the same data again.
2. When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.
Register Settings
Address *
H'FFB0
H'FFB1
H'FFB2
H'FFB3
H'FFB4
H'FFB5
H'FFB6
1
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
Bit 6
0
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
BRR3
TDR3
RDR3
Bit 3
1
0
PER
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
BRR1
RDR1
Bit 1
CKS1
CKE1 *
TDR1
0
—
2
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF