DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 642

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency ( )
when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, and figure
19.6 shows the external clock input timing. Figure 19.7 shows the external clock output
stabilization delay timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 19.3 Clock Timing
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
Note: * t
Rev. 3.00 Mar 21, 2006 page 612 of 814
REJ09B0302-0300
EXTAL
DEXT
includes 10 t
cyc
Figure 19.6 External Clock Input Timing
of RES pulse width (t
t
Symbol Min
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
t
EXr
*
t
EXH
15
15
—
—
0.4
80
0.4
80
500
V
V
CC
CC
DEXT
= 3.0V to 3.6V
= 5.0 V ± 10%
RESW
) has passed after the clock input. The system
DEXT
V
0.3 V
CC
Max
—
—
5
5
0.6
—
0.6
—
—
).
t
EXf
, while the clock output is unstable.
0.7
t
EXL
Unit
ns
ns
ns
ns
t
ns
t
ns
µs
cyc
cyc
Test Conditions
Figure 19.6
Figure 19.7
< 5 MHz
< 5 MHz
5 MHz
5 MHz
V
CC
Figure 21.4
0.5