DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 272

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 DMA Controller
8.6.6
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.
8.6.7
Table 8.14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 8.14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
Rev. 3.00 Mar 21, 2006 page 242 of 814
REJ09B0302-0300
When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then
clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.
It is possible to find whether a transfer was halted in the middle of a block by checking the
block size counter. If the block size counter does not have its initial value, the transfer was
halted in the middle of a block.
If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The
activation request is not held pending.
While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does
not accept activating interrupt requests. If an activating interrupt occurs in this state, the
DMAC does not operate and does not hold the transfer request pending internally. Neither is a
CPU interrupt requested.
For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating
interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See
section 8.6.5, Note on Activating DMAC by Internal Interrupts.
When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted
in the middle of a block transfer, the rest of the block is transferred when the next transfer
request occurs. Otherwise, the next block is transferred when the next transfer request occurs.
NMI Interrupts and Block Transfer Mode
Memory and I/O Address Register Values
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)