DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 498

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
Rev. 3.00 Mar 21, 2006 page 468 of 814
REJ09B0302-0300
Transmitting Serial Data (Asynchronous Mode)
Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure
to follow.
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit to 0 in SCR
in TDR and clear TDRE
Write transmit data
Start transmitting
Clear DR bit to 0,
set DDR bit to 1
flag to 0 in SSR
Output break
transmitted?
TDRE = 1?
TEND = 1?
Initialize
All data
signal?
Figure 13.5 Sample Flowchart for Transmitting Serial Data
End
Yes
Yes
Yes
Yes
No
No
No
No
1
2
3
4
1. SCI initialization: the transmit data output function of
2. SCI status check and transmit data write: read SSR,
3. To continue transmitting serial data: after checking
4. To output a break signal at the end of serial
the TxD pin is selected automatically. After the TE bit
is set to 1, one frame of 1 is output, then transmission
is possible.
check that the TDRE flag is 1, then write transmit data
in TDR and clear the TDRE flag to 0.
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE flag to
0. When the DMAC is activated by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the
TDRE flag is checked and cleared automatically.
transmission: set the DDR bit to 1 and clear the DR
bit to 0 (DDR and DR are I/O port registers), then
clear the TE bit to 0 in SCR.