DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 616

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
5. The period for which the P1 bit in FLMCR1 or the P2 bit in FLMCR2 is set (the write
Table 18.7 Wait Time after P Bit Setting
Item
Wait time after P
bit setting
Note: * Additional programming processing is necessary only when the reprogramming loop count
6. The program/program-verify flowchart for the H8/3052BF is shown in figure 18.12.
Rev. 3.00 Mar 21, 2006 page 586 of 814
REJ09B0302-0300
b. After write pulse application, a verify-read is performed in program-verify mode, and
c. If programming of other bits is incomplete in the 128 bytes, reprogramming process should
pulse width) should be changed according to the degree of progress through the
program/program-verify procedure. For detailed wait time specifications, see section
21.2.5, Flash Memory Characteristics.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown in
tables 18.8 and 18.9.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
program/program-verify procedure is completed. In the H8/3052BF, the number of loops
in reprogramming processing is guaranteed not to exceed the maximum programming
count (N).
programming is judged to have been completed for bits read as 0. The following
processing is necessary for programmed bits.
When programming is completed at an early stage in the program/program-verify
procedure:
If programming is completed in the 1st to 6th reprogramming processing loop,
additional programming should be performed on the relevant bits. Additional
programming should only be performed on bits which first return 0 in a verify-read
in certain reprogramming processing.
When programming is completed at a late stage in the program/program-verify procedure:
If programming is completed in the 7th or later reprogramming processing loop, additional
programming is not necessary for the relevant bits.
be executed. If a bit for which programming has been judged to be completed is read as 1
in a subsequent verify-read, a write pulse should again be applied to that bit.
(n) is 1 to 6.
Symbol
t
sp
Conditions
When reprogramming loop count (n) is 1 to 6
When reprogramming loop count (n) is 7 or more
In case of additional programming processing *
Symbol
t
t
t
sp
sp
sp
30
200
10