DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 247

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.4.5
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 8.9 indicates the register functions in I/O mode.
Table 8.9
Register
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCRA to H'0000.
Figure 8.8 illustrates how normal mode operates.
23
23
15
Normal Mode
MARA
MARB
Register Functions in Normal Mode
ETCRA
0
0
0
Function
Source address
register
Destination
address register
Transfer counter
Initial Setting
Source address
Destination
address
Number of
transfers
Rev. 3.00 Mar 21, 2006 page 217 of 814
Section 8 DMA Controller
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer
REJ09B0302-0300

Related parts for DF3052BX25V