DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 233

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full
address mode when DTS2A and DTS1A are both set to 1.
Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.
Operations in these modes are described in sections 8.4.5, Normal Mode, and 8.4.6, Block
Transfer Mode.
DTCRB
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 3: DTIE
0
1
Bit 0: DTS0A
0
1
Bit
Initial value
Read/Write
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
DTME
R/W
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
Description
Normal mode
Block transfer mode
7
0
Reserved bit
R/W
—
6
0
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
DAID
R/W
5
0
DAIDE
R/W
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
4
0
Rev. 3.00 Mar 21, 2006 page 203 of 814
TMS
R/W
3
0
DTS2B
R/W
2
0
Data transfer select
2B to 0B
These bits select the data
transfer activation source
Section 8 DMA Controller
DTS1B
R/W
REJ09B0302-0300
1
0
(Initial value)
(Initial value)
DTS0B
R/W
0
0