DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 254

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 DMA Controller
Figure 8.12 shows a sample setup procedure for block transfer mode.
Rev. 3.00 Mar 21, 2006 page 224 of 814
REJ09B0302-0300
Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.
Set block transfer count
Set destination address
Block transfer mode
Block transfer mode
Set source address
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Set DTCRB (1)
Set DTCRA (1)
Set DTCRB (2)
Set DTCRA (2)
Set block size
Read DTCRB
Read DTCRA
Figure 8.12 Block Transfer Mode Setup Procedure (Example)
1
2
3
4
5
6
7
8
9
10
1. Set the source address in MARA.
2. Set the destination address in MARB.
3. Set the block transfer count in ETCRB.
4. Set the block size (number of bytes or words) in
5. Set the DTCRB bits as follows.
6. Set the DTCRA bits as follows.
7. Read DTCRB with DTME cleared to 0.
8. Set the DTME bit to 1 in DTCRB.
9. Read DTCRA with DTE cleared to 0.
10. Set the DTE bit to 1 in DTCRA to enable the
both ETCRAH and ETCRAL.
• Clear the DTME bit to 0.
• Set the DAID and DAIDE bits to select whether
• Set or clear the TMS bit to make the block area
• Select the DMAC activation source with bits
• Clear the DTE to 0.
• Select byte size or word size with the DTSZ bit.
• Set the SAID and SAIDE bits to select whether
• Set or clear the DTIE bit to enable or disable
• Set bits DTS2A to DTS0A all to 1 to select
transfer.
MARB is incremented, decremented, or held
fixed.
the source or destination.
DTS2B to DTS0B.
MARA is incremented, decremented, or held
fixed.
the CPU interrupt at the end of the transfer.
block transfer mode.