DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 559

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 0—Reserved: Do not set to 1.
15.3
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15.2 shows the data flow for access to an A/D data register.
CPU Interface
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
Upper-byte read
Lower-byte read
CPU
(H'AA)
CPU
(H'40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Rev. 3.00 Mar 21, 2006 page 529 of 814
ADDRnL
ADDRnL
(H'40)
(H'40)
TEMP
(H'40)
TEMP
(H'40)
Module data bus
Module data bus
Section 15 A/D Converter
(n = A to D)
(n = A to D)
REJ09B0302-0300