DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 365

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
0
1
2
3
4
Bit
Initial value
Read/Write
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register input capture and compare match interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
—
—
7
1
—
—
6
1
Reserved bits
Function
Enables or disables interrupt requests.
—
—
5
1
—
—
4
1
Overflow interrupt enable
Enables or disables OVF
interrupts
Section 10 16-Bit Integrated Timer Unit (ITU)
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Rev. 3.00 Mar 21, 2006 page 335 of 814
—
—
3
1
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
OVIE
R/W
2
0
IMIEB
R/W
1
0
REJ09B0302-0300
IMIEA
R/W
0
0