DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 92

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 MCU Operating Modes
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so
that the waiting time will be at least 7 ms at the system clock rate. For further information about
waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software
Standby Mode.
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Rev. 3.00 Mar 21, 2006 page 62 of 814
REJ09B0302-0300
Bit 6: STS2
0
1
Bit 3: UE
0
1
Bit 2: NMIEG
0
1
Bit 0: RAME
0
1
Bit 5: STS1
0
1
0
1
Description
UI bit in CCR is used as an interrupt mask bit
UI bit in CCR is used as a user bit
Description
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
Description
On-chip RAM is disabled
On-chip RAM is enabled
Bit 4: STS0
0
1
0
1
0
1
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 1,024 states
Illegal setting
Description
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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