DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 360

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Rev. 3.00 Mar 21, 2006 page 330 of 814
REJ09B0302-0300
Bit 6: CCLR1
0
1
Bit 4: CKEG1
0
1
Bit 2: TPSC2
0
1
2. Selected in TSNC.
compare register, and by input capture when the general register functions as an input
capture register.
Bit 5: CCLR0
0
1
0
1
Bit 3: CKEG0
0
1
Bit 1: TPSC1
0
1
0
1
Description
TCNT is not cleared
TCNT is cleared by GRA compare match or input
capture *
TCNT is cleared by GRB compare match or input
capture *
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers *
Description
Count rising edges
Count falling edges
Count both edges
Bit 0: TPSC0
0
1
0
1
0
1
0
1
1
1
Description
Internal clock:
Internal clock: /2
Internal clock: /4
Internal clock: /8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
2
(Initial value)
(Initial value)
(Initial value)

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