DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 606

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
Rev. 3.00 Mar 21, 2006 page 576 of 814
REJ09B0302-0300
1
2
3
4
5
6
7
8
9
sends H'AA and receives two bytes
of the byte count (N) of the program
number of bytes to be sent (N = N – 1)
host to indicate end of adjustment
(H'FFE710) and executes the user
continuously at prescribed bit rate
transmits one byte of H'00 data to
After bit rate adjustment, this LSI
transferred to the on-chip RAM
program transferred to the RAM
of H'00 data transmitted by host
and sets value in bit rate register
Host confirms normal reception
indication (H'00), and transmits
This LSI calculates the remaining
Set pins to boot program mode
This LSI measures low period
After receiving H'55, this LSI
the flashmemory user area.
After sending H'AA, this LSI
(H'FFDF10 to H'FFE70F),
This LSI transfers the user
this LSI checks the data in
branches to the RAM area
Host transfers data (H'00)
of bit rate adjustment end
This LSI calculates bit rate
RAM boot program area
and execute reset-start
After branching to the
one byte of H'55 data
program to RAM
All data = H'FF?
end byte count
Transfer
N = 0?
Start
Figure 18.7 Boot Mode Execution Procedure
Yes
Yes
*2
Erase all blocks of flash
No
No
*1
memory
*3
1. Set this LSI to the boot mode and reset starts the LSI.
2. Set the host to the prescribed bit rate (4800, 9600,
3. This LSI repeatedly measures the RXD1 pin Low
4. At the end of SCI bit rate adjustment, this LSI sends
5. Check if the host normally received the one byte bit
6. After H'55 is sent, the host receives H'AA and sends
7. This LSI sequentially writes the received user program
8. Before executing the transferred user program, this LSI
9. After sending H'AA, this LSI branches to the on-chip
Notes: 1. The RAM area that can be used by the user is
19200) and consecutively send H'00 data in 8-bit data,
1 stop bit format.
period and calculates the asynchronous
communication bit rate at which the host performs
transfer.
one byte of H'00 data to signal the end of adjustment.
rate adjustment end signal sent from this LSI and sent
one byte of H'55 data.
the byte count of the user program that is transferred to
this LSI. Send the 2-byte count in upper byte and lower
byte order. Then sequentially send the program set by
the user. This LSI sequentially sends (echo back) each
byte of the received byte count and user program to the
host as verification data.
to the on-chip RAM area (H'FFE710 to H'FFFF0F).
checks if data was written to flash memory after control
branched to the RAM boot program area (H'FFDF10). If
data was already written to flash memory, all the blocks
are erased.
RAM area (H'FFE710) and executes the user program
written to that area.
2. Set the part that controls the user program
3. When a memory cell malfunctions and cannot
6 kbyte. Set the transfer byte count to within 6
kbyte. Always send the 2-byte transfer byte
count in upper byte and lower byte order.
Transfer byte count example: For 256 bytes
(H'0100), upper byte H'01, lower byte H'00.
flash memory at the program according to the
flash memory programming/erase algorithms
described later.
be erased, this LSI sends one H'FF byte as an
erase error and stops the erase operation and
subsequent operations.