DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 618

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
Rev. 3.00 Mar 21, 2006 page 588 of 814
REJ09B0302-0300
Figure 18.12 Program/Program-Verify Flowchart (128-Byte Programming)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
Note: Use a 10
Note 6: Write Pulse Width
Reprogram Data Computation Table
Number of Writes n
Original Data
Clear PSU1 (2) bit in FLMCR1 (2)
2. Verify data is read in 16-bit (W) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
4. A 128-byte area for storing program data and a 128-byte area for storing reprogram data must be provided in RAM.
5. A write pulse of 30 µs or 200 µs should be applied according to the progress of the programming operation. See Note 6 for the pulse widths. When writing of additional-
7. The wait times and value of N are shown in section 21.2.5, Flash Memory.
Write pulse application subroutine
Clear P1 (2) bit in FLMCR1 (2)
(D)
1000
Set P1 (2) bit in FLMCR1 (2)
0
0
1
1
Set PSU1 (2) in FLMCR1(2)
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area are modified as programming proceeds.
programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
Reprogram data storage
Sub-Routine Write Pulse
Additional-programming
Program data storage
data storage area
area (128 bytes)
area (128 bytes)
µ
Wait (tspsu)
Wait (tcpsu)
s write pulse for additional programming.
(128 bytes)
WDT enable
Wait (tsp)
Wait (tcp)
Disable WDT
RAM
End Sub
Verify Data
(V)
Write Time (tsp) µsec
0
1
0
1
µ
µ
µ
s
s
µ
s
s
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
Reprogram Data
(X)
Increment address
1
0
1
1
*
*
*
*
7
5
7
7
*
7
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
NG
Comments
Transfer reprogram data to reprogram data area
Additional-programming data computation
Write Pulse (Additional programming)
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Clear SWE1 (2) bit in FLMCR1 (2)
Write 128-byte data in RAM reprogram
Set SWE1 (2) bit in FLMCR1 (2)
H'FF dummy write to verify address
Clear PV1 (2) bit in FLMCR1 (2)
data area and reprogram data area
additional-programming data area
Set PV1 (2) bit in FLMCR1 (2)
Reprogram data computation
data verification completed?
Start of programming
End of programming
Wait (tsswe)
Wait (tcswe)
Wait (tspvr)
Read verify data
Wait (tspv)
Wait (tcpv)
OK
OK
Write data =
Write pulse
verify data?
OK
128-byte
START
m = 0 ?
6 n ?
6 n ?
m= 0
n= 1
Additional-Programming Data Computation Table
Reprogram Data
OK
OK
Sub-Routine-Call
Sub-Routine-Call
µ
µ
µ
µ
µ
s
s
s
(X')
s
s
0
0
1
1
NG
NG
NG
Verify Data
*
NG
*
*
*
7
*
*
(V)
See Note 6 for pulse width
7
7
2
3
7
0
1
0
1
*
*
*
4
4
1
Clear SWE1 (2) bit in FLMCR1 (2)
*
*
m= 1
4
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Programming Data (Y)
Programming failure
Wait (tcswe)
Additional-
0
1
1
1
n
N?
OK
µ
*
s
7
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
NG
n
Comments
n + 1
*
Reprogram
7