DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 535

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.3
Figure 14.3 shows the data format of the smart card interface. In receive mode, parity is checked
once per frame. If a parity error is detected, an error signal is returned to the transmitting device to
request retransmission. In transmit mode, the error signal is sampled and the same data is
retransmitted if the error signal is low.
The operating sequence is as follows.
1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level
2. To start transmitting a frame of data, the transmitting device transmits a low start bit (Ds),
3. Next, in the smart card interface, the transmitting device returns the data line to the high-
4. The receiving device performs a parity check. If there is no parity error, the receiving device
No parity error
Parity error
Ds:
D0 to D7:
Dp:
DE:
through a resistor.
followed by eight data bits (D0 to D7) and a parity bit (Dp).
impedance state. The data line is pulled up to the high level through a resistor.
waits to receive the next data. If a parity error is present, the receiving device outputs a low
error signal (DE) to request retransmission of the data. After outputting the error signal for a
Ds
Ds
Data Format
Start bit
Data bits
Parity bit
Error signal
D0
D0
D1
D1
Figure 14.3 Smart Card Interface Data Format
Output from transmitting device
Output from transmitting device
D2
D2
D3
D3
D4
D4
D5
D5
Rev. 3.00 Mar 21, 2006 page 505 of 814
D6
D6
Section 14 Smart Card Interface
D7
D7
Dp
Dp
REJ09B0302-0300
Output from
receiving device
DE

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