DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 236

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 DMA Controller
8.4
8.4.1
Table 8.5 summarizes the DMAC modes.
Table 8.5
Transfer Mode
Short address
mode
Full address
mode
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of transfers.
One 24-bit address and one 8-bit address are specified. The transfer direction is determined
automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
Repeat Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. When the designated number of transfers are completed, the initial address and
counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
Rev. 3.00 Mar 21, 2006 page 206 of 814
REJ09B0302-0300
Operation
Overview
DMAC Modes
I/O mode
Idle mode
Repeat mode
Normal mode
Block transfer
mode
Activation
Compare match/input
capture A interrupt from
ITU channels 0 to 3
Transmit-data-empty and
receive-data-full interrupts
from SCI channel 0
External request
Auto-request
External request
Compare match/input
capture A interrupt from ITU
channels 0 to 3
External request
Notes
Up to four channels can
operate independently
Only the B channels
support external requests
A and B channels are
paired; up to two channels
are available
Burst mode or cycle-steal
mode can be selected for
auto-requests