DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 513

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial clock
Serial data
TDRE
TEND
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
4. After the end of serial transmission, the SCK pin is held in a constant state.
Figure 13.17 shows an example of SCI transmit operation.
recognizes that TDR contains new data, and loads this data from TDR into TSR.
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty
interrupt (TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB,
holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end
interrupt (TEI) is requested at this time.
TXI
request
Figure 13.17 Example of SCI Transmit Operation
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
Bit 0
Transmit
direction
Bit 1
1 frame
Bit 7
TXI
request
Section 13 Serial Communication Interface
Rev. 3.00 Mar 21, 2006 page 483 of 814
Bit 0
Bit 1
Bit 6
REJ09B0302-0300
Bit 7
TEI
request