DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 449

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3.5
TPC output can be triggered by ITU input capture as well as by compare match. If GRA, and GRB
functions as an input capture register in the ITU channel selected in TPCR, TPC output will be
triggered by the input capture signal. Figure 11.8 shows the timing.
TIOC pin
Input capture
signal
NDR
DR
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and
G2CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the
output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping
output. Output data H'95 is written in NDRB.
The timer counter in this ITU channel is started. When compare match B occurs, outputs
change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change
from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the
next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59,
H'56, H'95… at successive IMFA interrupts. If the DMAC is set for activation by this
interrupt, pulse output can be obtained without loading the CPU.
TPC Output Triggering by Input Capture
Figure 11.8 TPC Output Triggering by Input Capture (Example)
Section 11 Programmable Timing Pattern Controller
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