DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 24

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3 Operation........................................................................................................................... 413
11.4 Usage Notes ...................................................................................................................... 420
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 423
12.2 Register Descriptions ........................................................................................................ 425
12.3 Operation........................................................................................................................... 430
12.4 Interrupts ........................................................................................................................... 434
12.5 Usage Notes ...................................................................................................................... 434
Section 13 Serial Communication Interface
13.1 Overview........................................................................................................................... 435
Rev. 3.00 Mar 21, 2006 page xxii of xxviii
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 401
11.2.2 Port A Data Register (PADR) .............................................................................. 401
11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 402
11.2.4 Port B Data Register (PBDR) .............................................................................. 402
11.2.5 Next Data Register A (NDRA) ............................................................................ 403
11.2.6 Next Data Register B (NDRB)............................................................................. 405
11.2.7 Next Data Enable Register A (NDERA).............................................................. 407
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 408
11.2.9 TPC Output Control Register (TPCR) ................................................................. 409
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 411
11.3.1 Overview.............................................................................................................. 413
11.3.2 Output Timing...................................................................................................... 414
11.3.3 Normal TPC Output............................................................................................. 415
11.3.4 Non-Overlapping TPC Output ............................................................................. 417
11.3.5 TPC Output Triggering by Input Capture ............................................................ 419
11.4.1 Operation of TPC Output Pins ............................................................................. 420
11.4.2 Note on Non-Overlapping Output........................................................................ 420
12.1.1 Features................................................................................................................ 423
12.1.2 Block Diagram ..................................................................................................... 424
12.1.3 Register Configuration......................................................................................... 424
12.2.1 Timer Counter (TCNT)........................................................................................ 425
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 426
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 428
12.2.4 Notes on Register Access..................................................................................... 429
12.3.1 Watchdog Timer Operation ................................................................................. 430
12.3.2 Interval Timer Operation ..................................................................................... 431
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 432
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 433
............................................................................................. 423
................................................................ 435