DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 482

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The
MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or
when the SCI is not transmitting.
13.2.8
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
Initial value
Read/Write
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. The two SCI channels have independent baud rate generator control, so different values can
be set in the two channels.
Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of
BRR settings in synchronous mode.
Rev. 3.00 Mar 21, 2006 page 452 of 814
REJ09B0302-0300
Bit 1: MPB
0
1
Bit 0: MPBT
0
1
previous value.
Bit Rate Register (BRR)
R/W
7
1
Description
Multiprocessor bit value in receive data is 0 *
Multiprocessor bit value in receive data is 1
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
(Initial value)
(Initial value)
R/W
0
1