DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 546

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Smart Card Interface
Examples of Operation in GSM Mode: When switching between smart card interface mode and
software standby mode, use the following procedures to maintain the clock duty cycle.
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
Rev. 3.00 Mar 21, 2006 page 516 of 814
REJ09B0302-0300
Switching from smart card interface mode to software standby mode
1. Set the P9
2. Write 0 to the TE and RE bits in the serial control register (SCR) to stop transmit/receive
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock
5. Write H'00 to the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
Returning from software standby mode to smart card interface mode
1. Clear the software standby state.
2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software
3. Set smart card interface mode and output the clock. Clock signal generation is started with
potential.
output state in software standby mode.
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
output is fixed at the specified level.
standby (the current P9
the normal duty cycle.
Figure 14.9 Procedure for Stopping and Restarting the Clock
4
(1)(2)(3)
data register (DR) and data direction register (DDR) to the values for the fixed
Normal operation
4
pin state).
(4) (5)(6)
Software standby
mode
(1) (2)(3)
Normal operation