DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 26

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 A/D Converter
15.1 Overview........................................................................................................................... 521
15.2 Register Descriptions ........................................................................................................ 525
15.3 CPU Interface.................................................................................................................... 529
15.4 Operation........................................................................................................................... 530
15.5 Interrupts ........................................................................................................................... 536
15.6 Usage Notes ...................................................................................................................... 536
Section 16 D/A Converter
16.1 Overview........................................................................................................................... 543
16.2 Register Descriptions ........................................................................................................ 546
16.3 Operation........................................................................................................................... 549
16.4 D/A Output Control .......................................................................................................... 550
Section 17 RAM
17.1 Overview........................................................................................................................... 551
17.2 System Control Register (SYSCR) ................................................................................... 553
17.3 Operation........................................................................................................................... 554
Section 18 ROM
Rev. 3.00 Mar 21, 2006 page xxiv of xxviii
15.1.1 Features................................................................................................................ 521
15.1.2 Block Diagram ..................................................................................................... 522
15.1.3 Pin Configuration................................................................................................. 523
15.1.4 Register Configuration......................................................................................... 524
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 525
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 526
15.2.3 A/D Control Register (ADCR) ............................................................................ 528
15.4.1 Single Mode (SCAN = 0) .................................................................................... 530
15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 532
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 534
15.4.4 External Trigger Input Timing ............................................................................. 535
16.1.1 Features................................................................................................................ 543
16.1.2 Block Diagram ..................................................................................................... 544
16.1.3 Pin Configuration................................................................................................. 545
16.1.4 Register Configuration......................................................................................... 545
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 546
16.2.2 D/A Control Register (DACR) ............................................................................ 546
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 548
17.1.1 Block Diagram ..................................................................................................... 552
17.1.2 Register Configuration......................................................................................... 553
.................................................................................................................. 551
.................................................................................................................. 555
................................................................................................. 521
................................................................................................. 543