DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 624

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
18.8.3
In error protection, an error is detected when H8/3052BF runaway occurs during flash memory
programming/erasing *
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the H8/3052BF malfunctions during flash memory programming/erasing, the FLER bit is set to
1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and
EBR2 settings *
error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or
E2 bit. However, PV1, PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to
verify mode. *
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
4. When the CPU releases the bus to the DMAC during programming/erasing
Error protection is released only by a power-on reset and in hardware standby mode.
Notes: 1. State in which the P1 bit or E1 bit in FLMCR1, or the P2 bit or E2 bit in FLMCR2, is
Rev. 3.00 Mar 21, 2006 page 594 of 814
REJ09B0302-0300
(including vector read and instruction fetch)
programming/erasing
2. It is possible to perform a program-verify operation on the 128 bytes being
3. FLMCR1, FLMCR2, EBR1, and EBR2 can be written to. However, the registers are
Error Protection
set to 1. Note that NMI input is disabled in this state.
programmed, or an erase-verify on the block being erased.
initialized if a transition is made to software standby mode while in the error-protected
state.
2
3
are retained, but program mode or erase mode is aborted at the point at which the
1
, or operation is not performed in accordance with the program/erase