DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 431

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.2
11.2.1
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
Initial value
Read/Write
Port A is multiplexed with pins TP
be set to 1. For further information about PADDR, see section 9.11, Port A.
11.2.2
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
Initial value
Read/Write
Note:
For further information about PADR, see section 9.11, Port A.
*
Bits selected for TPC output by NDERA settings become read-only bits.
Register Descriptions
Port A Data Direction Register (PADDR)
Port A Data Register (PADR)
PA DDR
R/(W)
PA
7
W
0
7
0
7
7
*
PA DDR
R/(W)
PA
6
W
0
6
0
6
6
*
7
PA DDR
to TP
R/(W)
PA
5
W
0
5
0
5
5
0
*
. Bits corresponding to pins used for TPC output must
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
PA DDR
Section 11 Programmable Timing Pattern Controller
R/(W)
PA
4
W
0
4
0
4
4
*
PA DDR
R/(W)
Rev. 3.00 Mar 21, 2006 page 401 of 814
PA
3
W
0
3
0
3
3
*
PA DDR
R/(W)
PA
2
W
0
2
0
2
2
*
PA DDR
R/(W)
PA
1
W
0
1
0
1
REJ09B0302-0300
1
*
PA DDR
R/(W)
PA
0
W
0
0
0
0
0
*