DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 604

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
18.6
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
18.5. For a diagram of the transitions to the various flash memory modes, see figure 18.2.
Table 18.5 Setting On-Board Programming Modes
Mode
Boot mode
User program mode
Notes: 1. For the high-level application timing, see items 6 and 7 in Notes on Use of Boot Mode.
18.6.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI channel to be used is set to asynchronous mode.
When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program
built into the LSI is started and the programming control program prepared in the host is serially
transmitted to the LSI via the SCI. In the LSI, the programming control program received via the
SCI is written into the programming control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and the
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 18.6, and the boot mode execution
procedure in figure 18.7.
Rev. 3.00 Mar 21, 2006 page 574 of 814
REJ09B0302-0300
2. In boot mode, the inverse of the MD
3. In boot mode, the mode control register (MDCR) can be used to monitor the status of
On-Board Programming Modes
Boot Mode
modes 5, 6, and 7, in the same way as in normal mode.
Mode 5
Mode 6
Mode 7
Mode 5
Mode 6
Mode 7
FWE
1*
2
MD2
0*
0*
0*
1*
1*
1*
setting should be input.
MD1
0
1
1
0
1
1
MD0
1
0
1
1
0
1
Notes
0: V
1: V
IL
IH