DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 371

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
non-overlapping complementary waveforms. When complementary PWM mode is selected
GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and
TIOCA
TCNT3 and TCNT4 operate as up/down-counters.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-
counter.
Buffering
10.4.2
Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR),
the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-
running or periodic.
If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
If the general register is an input capture register
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction.
Reset-synchronized PWM mode
The buffer register value is transferred to the general register at GRA3 compare match.
Sample setup procedure for counter
Figure 10.14 shows a sample procedure for setting up a counter.
3
, TIOCB
Basic Functions
3
, TIOCA
4
, TOCXA
4
, TIOCB
4
, and TOCXB
Section 10 16-Bit Integrated Timer Unit (ITU)
Rev. 3.00 Mar 21, 2006 page 341 of 814
4
function as PWM output pins.
REJ09B0302-0300