DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 44

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Type
System control
Interrupts
Address bus
Data bus
Bus control
Rev. 3.00 Mar 21, 2006 page 14 of 814
REJ09B0302-0300
Symbol
RES
FWE
STBY
BREQ
BACK
NMI
IRQ
A
D
CS
AS
RD
HWR
LWR
WAIT
23
15
7
to A
to D
5
to CS
to IRQ
0
0
0
0
Pin No.
63
10
62
59
60
64
17, 16,
90 to 87
97 to 100,
56 to 45,
43 to 36
34 to 23,
21 to 18
8, 97 to 99,
88 to 91
69
70
71
72
58
I/O
Input
Input
Input
Input
Output
Input
Input
Output
Input/
output
Output
Output
Output
Output
Output
Input
Reset input: When driven low, this pin
resets the chip
Flash write enable: Allows program mode
setting.
Standby: When driven low, this pin forces a
transition to hardware standby mode
Bus request: Used by an external bus
master to request the bus right
Bus request acknowledge: Indicates that
the bus has been granted to an external bus
master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable
interrupt request pins
Address bus: Outputs address signals
Data bus: Bidirectional data bus
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from
the external address space
High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D
Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Name and Function
7
15
to D
to D
0
).
8
).