DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 91

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD
MDS0 are read-only bits. The mode pin (MD
MDCR is read.
3.3
SYSCR is an 8-bit register that controls the operation of the H8/3052BF.
Bit
Initial value
Read/Write
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 20, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7: SSBY
0
1
2
to MD
System Control Register (SYSCR)
0
(the current operating mode). MDS2 to MDS0 correspond to MD
SSBY
Software standby
Enables transition to software standby mode
R/W
7
0
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
STS2
R/W
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
6
0
STS1
R/W
5
0
2
STS0
R/W
to MD
4
0
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
0
) levels are latched into these bits when
R/W
UE
3
1
Rev. 3.00 Mar 21, 2006 page 61 of 814
NMI edge select
Selects the valid edge
of the NMI input
NMIEG
Section 3 MCU Operating Modes
R/W
2
0
Reserved bit
1
1
2
RAM enable
Enables or
disables
on-chip RAM
REJ09B0302-0300
to MD
RAME
R/W
(Initial value)
0
1
0
. MDS2 to

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