DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 271

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 8.26 before and after setting the DTME bit to
1.
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next
interrupt does not occur before the DMA transfers end on all the activated channels. If the next
interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
Interrupt handling
Figure 8.26 Procedure for Enabling DMAC while On-Chip Supporting Module Is
by CPU
Yes
Clear selected interrupt’s
Set selected interrupt’s
Enabling of DMAC
Selected interrupt
DMAC operates
enable bit to 0
Enable DMAC
enable bit to 1
requested?
No
Operating (Example)
1
2
3
4
Rev. 3.00 Mar 21, 2006 page 241 of 814
1. While the DTE bit is cleared to
2. Clear the interrupt enable bit to
3. Enable the DMAC.
4. Enable the DMAC-activating
0, interrupt requests are sent
to the CPU.
0 in the interrupt-generating
on-chip supporting module.
interrupt.
Section 8 DMA Controller
REJ09B0302-0300