DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 225

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2.4
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
Bit
Initial value
Read/Write
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7: DTE
0
1
In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial
transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH
reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
The ETCRs are not initialized by a reset or in standby mode.
Data transfer enable
Enables or disables
data transfer
Data Transfer Control Registers (DTCR)
DTE
R/W
7
0
Data transfer size
Selects byte or
word size
Description
Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when
the specified number of transfers have been completed.
Data transfer is enabled
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
DTSZ
R/W
6
0
DTID
R/W
5
0
Repeat enable
Selects repeat
mode
RPE
R/W
4
0
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
DTIE
R/W
3
0
Rev. 3.00 Mar 21, 2006 page 195 of 814
DTS2
R/W
2
0
Data transfer select
These bits select the data
transfer activation source
Section 8 DMA Controller
DTS1
R/W
1
0
REJ09B0302-0300
DTS0
R/W
(Initial value)
0
0